The invention relates to a memory array.
A memory array of a DRAM of the prior art will be described below with reference to FIG. 5. MC0, MC1, . . . , MC(nxe2x88x921) and MCn denote memory cells, each of which comprises a switching transistor Q (a MOSFET) and a capacitor C which are connected in series. WL0, WL1, . . . , WL2n, and WL(2n+1) denote word lines for activating the memory cells MC0, MC1, . . . , MC(nxe2x88x921), and MCn, respectively. BL and BLB denote a pair of bit lines whose complementary logic voltages are interchanged during the writing of data. VL denotes a cell plate voltage line for applying a cell plate voltage Vcp (=Vcc/2) to the capacitors C of the memory cells MC0, MC1, . . . , MC(nxe2x88x921), and MCn. The cell plate voltage line VL is connected to a cell plate voltage generator circuit (not shown).
Each series circuit comprising the switching transistor Q (the MOSFET) and the capacitor C of each of the memory cells MC0, MC2, . . . , and MC(nxe2x88x921) is connected between the bit line BL and the cell plate voltage line VL. The respective control terminals (i.e., gates) of the switching transistors Q of the memory cells MC0, MC2, . . . , and MC(nxe2x88x921) are connected to the word lines WL0, WL2, . . . , and WL2n, respectively. In this case, the capacitors C are connected to the cell plate voltage line VL.
Each series circuit comprising the switching transistor Q and the capacitor C of each of the memory cells MC1, MC3, . . . , and MCn is connected between the bit line BLB and the cell plate voltage line VL. The respective control terminals (i.e., gates) of the switching transistors Q of the memory cells MC1, MC3, . . . , and MCn are connected to the word lines WL1, WL3, . . . , and WL(2n+1), respectively. In this case, the capacitors C are connected to the cell plate voltage line VL.
Furthermore, a sense amplifier SA is connected between the bit lines BL and BLB. An equalizer circuit EQ is also connected between the bit lines BL and BLB. The equalizer circuit EQ comprises MOSFETs Q1, Q2 and Q3. A bit line precharge voltage Vpr (=Vcc/2) is applied to the respective drains of the MOSFETs Q1 and Q2, and the respective sources of the MOSFETs Q1 and Q2 are connected to the bit lines BL and BLB, respectively. A drain and a source of the MOSFET Q3 are connected to the bit lines BL and BLB, respectively. The bit line precharge voltage Vpr is supplied to the bit lines BL and BLB, and a gate signal PEQ for equalizing the bit lines BL and BLB is applied to the respective gates of the MOSFETs Q1, Q2 and Q3.
Actually, a plurality of circuits of FIG. 5 configured as described above are provided, and the word lines WL0, WL1, . . . , WL2n, and WL(2n+1), a line to which the bit line precharge voltage Vpr is supplied, and a line to which the gate signal PEQ is supplied are common to the plurality of circuits. The cell plate voltage lines VL of a plurality of circuits are connected to a common cell plate voltage generator circuit.
Next, the operation of the memory array shown in FIG. 5 will be described with reference to FIG. 6. When a voltage of the word line WL0 changes to high level as shown in FIG. 6A and thus the memory cell MC0 is activated or more specifically the MOSFET Q of the memory cell MC0 is turned on, a read operation and a write operation are performed as discussed below. Data xe2x80x9c0xe2x80x9d stored in the capacitor C of the memory cell MC0 is supplied to the sense amplifier SA through the MOSFET Q and the bit line BL and is then amplified and latched by the sense amplifier SA, and thus a voltage of the bit line BL changes to 0 (V) as shown in FIG. 6B. After that, data xe2x80x9c1xe2x80x9d is inversely written in the sense amplifier SA and is then amplified and latched by the sense amplifier SA, and thus the voltage of the bit line BL is inverted into Vcc (V) as shown in FIG. 6B. Thus, the data xe2x80x9c1xe2x80x9d is rewritten in the capacitor C of the memory cell MC0 through the bit line BL and the MOSFET Q of the memory cell MC0.
After the end of rewriting, the voltage of the word line WL0 changes from high level to low level as shown in FIG. 6A, and simultaneously, the gate signal PEQ changes from low level to high level as shown in FIG. 6D. Thus, the MOSFETs Q1 to Q3 constituting the equalizer circuit EQ are switched from the off state to the on state, and thus, both the voltages of the bit lines BL and BLB are equalized and precharged at the bit line precharge voltage Vpr (=Vcc/2) as shown in FIG. 6B.
Incidentally, when the voltage of the word line WL0 changes to high level as shown in FIG. 6A, a voltage of the word line WL1 also changes to high level, and thus the voltage of the bit line BL becomes reverse with respect to the voltage of the bit line BLB as shown in FIG. 6B in a condition in which data is latched by the sense amplifier SA during reading and writing.
As described above, data stored in the activated memory cell is read out, and the data is supplied to the sense amplifier SA through the bit line and is then amplified and latched by the sense amplifier SA. Thereafter, data is inversely written in the sense amplifier SA and is then amplified and latched by the sense amplifier SA. Thus, the high and low voltage amplitudes of the bit lines BL and BLB are interchanged, and then the following or next operation is performed. More specifically, coupling noises are produced on the cell plate voltage line VL through the capacitor of the activated memory cell, and thus the cell plate voltage Vcp of the cell plate voltage line VL changes from Vcp=Vcc/2 to Vcp=(Vcc/2)xc2x1dvcp (provided that 0 less than dVcp less than Vcc/2). The cell plate voltage Vcp of the memory array shown in FIG. 5 changes to Vcp=(Vcc/2)+dVcp as shown in FIG. 6C.
In the memory array shown in FIG. 5, a pair of the bit lines BL and BLB is provided, but generally a plurality of pairs of the bit lines BL and BLB are provided. In this case, the cell plate voltage lines VL corresponding to the pairs of the bit lines BL and BLB are connected to a common cell plate voltage generator circuit. The cell plate voltage Vcp changes from Vcp=Vcc/2 to Vcp=(Vcc/2)+dVcpxc3x97axe2x88x92dVcpxc3x97b, where xe2x80x9caxe2x80x9d denotes the number of bit lines whose voltages change from 0 (V) to Vcc (V) and xe2x80x9cbxe2x80x9d denotes the number of bit lines whose voltages change from Vcc (V) to 0 (V) provided that a plurality of bit lines are connected to the same word line and are connected to a plurality of memory cells which are which are simultaneously activated.
In view of the foregoing, the invention is intended to provide a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. The memory array includes a plurality of pairs of first and second bit lines whose complementary logic voltages are interchanged during data writing; a plurality of pairs of first and second word lines; a common cell plate voltage line; a first memory cell connected to each first bit line, each first word line and the common cell plate voltage line; a second memory cell connected to each second bit line, each second word line and the common cell plate voltage line; and a sense amplifier connected between the first and second bit lines of each pair, wherein a plurality of the first and second memory cells are arranged in a matrix form.
According to a first aspect of the invention, there is provided a memory array including a plurality of pairs of first and second bit lines whose complementary logic voltages are interchanged during data writing; a plurality of pairs of first and second word lines; a common cell plate voltage line; a first memory cell connected to each first bit line, each first word line and the common cell plate voltage line; a second memory cell connected to each second bit line, each second word line and the common cell plate voltage line; and a sense amplifier connected between the first and second bit lines of each pair, wherein a plurality of the first and second memory cells are arranged in a matrix form, the memory array comprising: first and second dummy word lines; a first dummy memory cell connected to each first bit line, the first dummy word line and the common cell plate voltage line; and a second dummy memory cell connected to each second bit line, the second dummy word line and the common cell plate voltage line, and wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell so as to write the first data in the first memory cell, and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell so as to write the second data in the second memory cell.
According to a second aspect of the invention, in the memory array according to the first aspect of the invention, the timing at which the first and second dummy word lines change from an active state to an inactive state is delayed by a predetermined time with respect to the timing at which the first and second word lines change from an active state to an inactive state.
According to a third aspect of the invention, the memory array according to the first aspect of the invention further comprises means for applying a precharge voltage to a midpoint of a connection between a switching transistor and a capacitor of each of the first and second dummy memory cells when the first and second word lines and the first and second dummy word lines change from an active state to an inactive state.
According to a fourth aspect of the invention, the memory array according to the first, second or third aspect of the invention is made of a dynamic RAM.